\section{Customizing the application}
\subsection{connection of the DMA FIFOs}
Wupper comes with an example application that is described in \ref{sec:ExampleApp}. The toplevel file for the user application is wupper\_oc\_top.vhd

If you want to customize the example application for your own needs, the application can be stripped down by removing the connections to toHostFifo\_* and fromHostFifo\_* signals and connecting them as required to newly created entities in the design. The application can be controlled and monitored by the records "registermap\_control" and "registermap\_monitor". These records contain all the read/write register and the read only registers respectively, the registers are defined in the file pcie\_package.vhd.

This file contains a read and a write port for a FIFO. This FIFO has a port width of 256 bit and is read or written at 250 MHz, resulting in a theoretical throughput of 60Gbit/s for PCIe Gen3x8 interfaces. For PCIe Gen4x8 or Gen3x16 interfaces (Virtex Ultrascale+, Versal Prime) the FIFO width is 512 bits and the theoretical throughput is around 120Gbit/s.

\subsection{Application specific registers}
Besides DMA memory reads and writes, the PCIe Engine also provides means to create a custom application specific register map. By default, the BAR2 register space is reserved for this purpose.

\begin{lstlisting}[language=VHDL, frame=single, caption=custom register types]
  -- Control Record
type register_map_control_type is record
STATUS_LEDS                    : std_logic_vector(7 downto 0);    -- Board GPIO Leds
I2C_WR                         : bitfield_i2c_wr_t_type;         -- House Keeping Controls and Monitors 
I2C_RD                         : bitfield_i2c_rd_t_type;         -- House Keeping Controls and Monitors 
INT_TEST                       : bitfield_int_test_t_type;       -- House Keeping Controls and Monitors 
DMA_BUSY_STATUS                : bitfield_dma_busy_status_t_type;  -- House Keeping Controls and Monitors 
WISHBONE_CONTROL               : bitfield_wishbone_control_w_type;  -- Wishbone 
WISHBONE_WRITE                 : bitfield_wishbone_write_t_type;  -- Wishbone 
WISHBONE_READ                  : bitfield_wishbone_read_t_type;  -- Wishbone 
LOOPBACK                       : std_logic_vector(7 downto 0);    -- for every DMA descriptor
-- 0: Generate data from a counter value
-- 1: Loop back data from FromHost to ToHost DMA

end record;
\end{lstlisting}

The VHDL files containing the registermap are not supposed to be modified by hand. Instead WupperCodeGen can be used.

Inside the source tree you will find the directory WupperCodeGenScripts containing the YAML file with application specific registers, and a set of scripts to generate VHDL sources, C++ headers and Latex and HTML documentation.
\begin{itemize}
	\item \textbf{registers-2.0.yaml: }This is the database of registers 
	\item \textbf{build-doc.sh }Run this script to generate the table of registers in \ref{App:Regmap}
	\item \textbf{build-firmware.sh }Regenerate the firmware (pcie\_control.vhd and pcie\_package.vhd) from the yaml file
	\item \textbf{build-software.sh }Regenerate the sources in software/regmap from the yaml file.

\end{itemize}

For more information see the documentation in software/wuppercodegen/doc

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